![]() ![]() My own code tend to have expected values but the connections to the output of these IP core modules give "z".įinal point: There are files associated with the creation of these IP core through megaWizard. Start simulating by choosing the top level module - loads and I can view the waveforms of some signals.Compile on modelSim, all files get green checks (indicating fine).Add existing files from my own project that is written in Verilog (a bunch of.Create new project under a new arbitrary directory.My procedure in setting up this simulation is as the following: ![]() I'm not sure if i'm missing any special steps here simulating the IP blocks. The input signals for these blocks such as clock, clk_en and aclr are set properly. I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim.Īll the instantiated IP blocks such as ALTFP_DIV, ALTFP_LOG, ALTFP_ADD_SUB are producing no outputs (result being "z").
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